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Section 4. Architecture
HIGHLIGHTS
This section of the manual contains the following major topics: 4.1 4.2 4.3 4.4 4.5 4.6 4.7 Introduction .................................................................................................................... 4-2 Clocking Scheme/Instruction Cycle ............................................................................... 4-5 Instruction Flow/Pipelining ............................................................................................. 4-6 I/O Descriptions ............................................................................................................. 4-7 Design Tips .................................................................................................................. 4-14 Related Application Notes............................................................................................ 4-15 Revision History ........................................................................................................... 4-16
4
Architecture
2000 Microchip Technology Inc.
DS39504A-page 4-1
PIC18C Reference Manual
4.1 Introduction
The high performance of the PIC18CXXX devices can be attributed to a number of architectural features commonly found in RISC microprocessors. These include: * * * * * * * * Harvard architecture Long Word Instructions Single Word Instructions Single Cycle Instructions Instruction Pipelining Reduced Instruction Set Register File Architecture Orthogonal (Symmetric) Instructions
Figure 4-2 shows a general block diagram for PIC18CXXX devices.
Harvard Architecture:
Harvard architecture has the program memory and data memory as separate memories which are accessed from separate buses. This improves bandwidth over traditional von Neumann architecture in which program and data are fetched from the same memory using the same bus. To execute an instruction, a von Neumann machine must make one or more (generally more) accesses across the 8-bit bus to fetch the instruction. Then data may need to be fetched, operated on and possibly written. As can be seen from this description, the bus can become extremely congested. With a Harvard architecture, the instruction is fetched in a single instruction cycle (all 16 bits). While the program memory is being accessed, the data memory is on an independent bus and can be read and written. These separated busses allow one instruction to execute, while the next instruction is fetched. A comparison of Harvard and von Neumann architectures is shown in Figure 4-1. Figure 4-1: Harvard vs. von Neumann Block Architectures
Harvard
von Neumann
Data Memory
CPU 8 16
Program Memory
CPU 8
Program and Data Memory
Long Word Instructions:
Long word instructions have a wider (more bits) instruction bus than the 8-bit data memory bus. This is possible because the two buses are separate. This allows instructions to be sized differently than the 8-bit wide data word and allows a more efficient use of the program memory, since the program memory width is optimized to the architectural requirements.
Single Word Instructions:
Single word instruction opcodes are 16-bits wide making it possible to have all but a few instructions be single word instructions. A 16-bit wide program memory access bus fetches a 16-bit instruction in a single cycle. With single word instructions, the number of words of program memory locations equals the number of instructions for the device. This means that all locations are valid instructions. Typically in the von Neumann architecture, most instructions are multi-byte. In general, a device with 4 Kbytes of program memory would allow approximately 2K of instructions. This 2:1 ratio is generalized and dependent on the application code. Since each instruction may take multiple bytes, there is no assurance that each location is a valid instruction.
DS39504A-page 4-2
2000 Microchip Technology Inc.
Section 4 Architecture
Double Word Instructions:
Some operations require more information then can be stored in the 16 bits of a program memory location. These operations require a double word instruction, and are therefore 32-bits wide. Instructions that require this second instruction word are: * Memory to memory move instruction (12 bits for each RAM address) - MOVFF SourceReg, DestReg * Literal value to FSR move instruction (12 bits for data and 2 bits for FSR to load) - LFSR FSR#, Address * Call and goto operations (20 bits for address) - CALL Address - GOTO Address The first word indicates to the CPU that the next program memory location is the additional information for this instruction and not an instruction. If the CPU tries to execute the second word of an instruction (due to a software modified PC pointing to that location as an instruction), the fetched data is executed as a NOP. Double word instruction execution is not split between the two TCY cycles by an interrupt request. That is, when an interrupt request occurs during the execution of a double word instruction, the execution of the instruction is completed before the processor vectors to the interrupt address. The interrupt latency is preserved.
Instruction Pipeline:
The instruction pipeline is a two-stage pipeline that overlaps the fetch and execution of instructions. The fetch of the instruction takes one TCY, while the execution takes another TCY. However, due to the overlap of the fetch of current instruction and execution of previous instruction, an instruction is fetched and another instruction is executed every TCY.
Single Cycle Instructions:
With the program memory bus being 16-bits wide, the entire instruction is fetched in a single machine cycle (TCY), except for double word instructions. The instruction contains all the information required and is executed in a single cycle. There may be a one cycle delay in execution if the result of the instruction modified the contents of the program counter. This requires the pipeline to be flushed and a new instruction to be fetched.
Two Cycle Instructions:
Double word instructions require two cycles to execute, since all the required information is in the 32 bits.
Reduced Instruction Set:
When an instruction set is well designed and highly orthogonal (symmetric), fewer instructions are required to perform all needed tasks. With fewer instructions, the whole set can be more rapidly learned.
4
Architecture
Register File Architecture:
The register files/data memory can be directly or indirectly addressed. All special function registers, including the program counter, are mapped in the data memory.
Orthogonal (Symmetric) Instructions:
Orthogonal instructions make it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of "special instructions" make programming simple yet efficient. In addition, the learning curve is reduced significantly. The Enhanced MCU instruction set uses only three non-register oriented instructions, which are used for two of the cores features. One is the SLEEP instruction, which places the device into the lowest power use mode. The second is the CLRWDT instruction, which verifies the chip is operating properly by preventing the on-chip Watchdog Timer (WDT) from overflowing and resetting the device. The third is the RESET instruction, which resets the device.
2000 Microchip Technology Inc.
DS39504A-page 4-3
PIC18C Reference Manual
Figure 4-2: General Enhanced MCU Block Diagram
Data Bus<8> PORTA Table Pointer<21> 8 21 21 Address Latch Program Memory (up to 2M Bytes) Data Latch 31 Level Stack 20
PCLATU PCLATH
21
Data Latch 8 8 Data RAM (up to 4K address reach) Address Latch PORTB 12 Address<12> 4
BSR
inc/dec logic
RA0 RA1 RA2 RA3 RA4 RA5 RA6
PCU PCH PCL Program Counter
12 FSR0 FSR1 FSR2 inc / dec logic
4 Bank0, F
RB0/INT0 RB1/INT1 RB2/INT2 RB3 RB<7:4> PORTC RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 PORTD RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 8 PORTE RE0 RE1 RE2 RE3 RE4 RE5 RE6 RE7
12
16
TABLELATCH
Decode
8
ROMLATCH
Instruction Register Instruction Decode & Control OSC2/CLKOUT OSC1/CLKIN Timing Generation Power-up Timer Oscillator Start-up Timer Power-on Reset 4X PLL Watchdog Timer Brown-out Reset 3 8 PRODH PRODL 8 x 8 Multiply W 8 8 ALU<8> 8
T1OSI T1OSO
BITOP 8
8
Precision Bandgap Reference
MCLR
VDD, VSS
PORTx Rx0 Rx1 Rx2 Rx3 Rx4 Rx5 Rx6 Rx7
Timer0
Timer1
Timer2
Timer3
A/D Converter Other Peripherals
CCP's
Enhanced CCP's
Master Synchronous Serial Port
Addressable USART
CAN
USB
Peripheral Modules (Note 1) Note 1: Many of the general purpose I/O pins are multiplexed with one or more peripheral module functions. The multiplexing combinations are device dependent.
DS39504A-page 4-4
2000 Microchip Technology Inc.
Section 4 Architecture
4.2 Clocking Scheme/Instruction Cycle
The clock input is internally divided by four to generate four non-overlapping quadrature clocks, namely Q1, Q2, Q3 and Q4. Internally, the program counter is incremented every Q1, and the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow are illustrated in Figure 4-3 and Example 4-1. Figure 4-3: Clock/Instruction Cycle
TCY1 Q1 Device Clock (OSC1 or T1OSCI) Q1 Q2 Q3 Q4 PC CLKOUT (RC mode)
Fetch INST (PC) Execute INST (PC-2) Fetch INST (PC+2) Execute INST (PC) Fetch INST (PC+4) Execute INST (PC+2)
TCY2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
TCY3 Q2 Q3 Q4
Q2
Internal phase clock
PC
PC+2
PC+4
4.2.1
Phase Lock Loop (PLL)
The clock input is multiplied by four by the PLL. Therefore, when it is internally divided by four, it provides an instruction cycle that is the same frequency as the external clock frequency. Four non-overlapping quadrature clocks, namely Q1, Q2, Q3 and Q4 are still generated internally. Internally, the program counter (PC) is incremented every Q1, and the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow are illustrated in Figure 4-4 and Example 4-1.
Figure 4-4: Clock/Instruction Cycle with PLL TCY1
Q1 PLL Output Q1 Q2 Q3 Q4 PC OSC2/CLKOUT (RC mode)
Fetch INST (PC) Execute INST (PC-2) Fetch INST (PC+2) Execute INST (PC) Fetch INST (PC+4) Execute INST (PC+2) PC PC+2 PC+4
4
TCY2 TCY3
Architecture
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Internal phase clock
2000 Microchip Technology Inc.
DS39504A-page 4-5
PIC18C Reference Manual
4.3 Instruction Flow/Pipelining
An "Instruction Cycle" consists of four Q cycles (Q1, Q2, Q3 and Q4). Fetch takes one instruction cycle, while decode and execute takes another instruction cycle. However, due to pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g. GOTO instruction), then an extra cycle is required to complete the instruction (See Example 4-1). The instruction fetch begins with the program counter incrementing in Q1. In the execution cycle, the fetched instruction is latched into the "Instruction Register (IR)" in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). Example 4-1 shows the operation of the two stage pipeline for the instruction sequence shown. At time TCY0, the first instruction is fetched from program memory. During TCY1, the first instruction executes, while the second instruction is fetched. During TCY2, the second instruction executes, while the third instruction is fetched. During TCY3, the fourth instruction is fetched, while the third instruction (CALL SUB_1) is executed. When the third instruction completes execution, the CPU forces the address of instruction four onto the Stack and then changes the Program Counter (PC) to the address of SUB_1. This means that the instruction that was fetched during TCY3 needs to be "flushed" from the pipeline. During TCY4, instruction four is flushed (executed as a NOP) and the instruction at address SUB_1 is fetched. Finally during TCY5, instruction five is executed and the instruction at address SUB_1 + 2 is fetched. Example 4-1: Instruction Pipeline Flow TCY0
1. MOVLW 55h 2. MOVWF PORTB 3. CALL SUB_1 4. BSF PORTA, BIT3 (Forced NOP)
TCY1 Execute 1 Fetch 2
TCY2 Execute 2 Fetch 3
TCY3
TCY4
TCY5
Fetch 1
Execute 3 Fetch 4 Flush Fetch SUB_1 Execute SUB_1 Fetch SUB_1 + 2
5. Instruction @ address SUB_1
Most instructions are single cycle. Program branches take two cycles, since the fetch instruction is "flushed" from the pipeline while the new instruction is being fetched and then executed.
DS39504A-page 4-6
2000 Microchip Technology Inc.
Section 4 Architecture
4.4 I/O Descriptions
Table 4-1 gives a brief description of device pins and the functions that may be multiplexed to a port pin. Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module's functional requirements may force an override of the data direction (TRIS bit) of the port pin (such as in the A/D and Comparator modules). Table 4-1: Pin Name A19 A18 A17 A16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 ALE I/O Descriptions Pin Type O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O Buffer Type -- -- -- -- TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL -- Description System bus address line 19 System bus address line 18 System bus address line 17 System bus address line 16 System bus address/data line 15 System bus address/data line 14 System bus address/data line 13 System bus address/data line 12 System bus address/data line 11 System bus address/data line 10 System bus address/data line 9 System bus address/data line 8 System bus address/data line 7 System bus address/data line 6 System bus address/data line 5 System bus address/data line 4 System bus address/data line 3 System bus address/data line 2 System bus address/data line 1 System bus address/data line 0 System bus address latch enable strobe Analog Input Channels
AN0 I Analog AN1 I Analog AN2 I Analog AN3 I Analog AN4 I Analog AN5 I Analog AN6 I Analog AN7 I Analog AN8 I Analog AN9 I Analog AN10 I Analog AN11 I Analog AN12 I Analog AN13 I Analog AN14 I Analog AN15 I Analog P P Analog Power AVDD Legend: TTL = TTL-compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels O = output PU = Weak internal pull-up I = input Analog = Analog input or output P = Power
4
Architecture
2000 Microchip Technology Inc.
DS39504A-page 4-7
PIC18C Reference Manual
Table 4-1: Pin Name AVSS BA0 CANRX CANTX0 CANTX1 CCP1 CCP2 CK CLKI CLKO I/O Descriptions (Continued) Pin Type P O I O O I/O I/O I/O I O Buffer Type P -- ST -- -- ST ST ST ST/CMOS -- Description Analog Ground System bus byte address 0 CAN bus receive pin CAN bus transmit CAN bus complimentary transmit or CAN bus bit time clock Capture1 input/Compare1 output/PWM1 output Capture2 input/Compare2 output/PWM2 output. USART Synchronous Clock, always associated with TX pin function (See related TX, RX, DT) External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKIN, OSC2/CLKOUT pins) Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. Always associated with OSC2 pin function. (See related OSC2, OSC1) Comparator A output Comparator B output
CMPA CMPB CS CVREF DT
O O I O I/O
-- -- TTL Analog ST
Chip select control for parallel slave port (See related RD and WR) Comparator voltage reference output USART Synchronous Data. Always associated RX pin function. (See related RX, TX, CK) Legend: TTL = TTL-compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels O = output PU = Weak internal pull-up I = input Analog = Analog input or output P = Power
DS39504A-page 4-8
2000 Microchip Technology Inc.
Section 4 Architecture
Table 4-1: Pin Name INT0 INT1 INT2 LB LVDIN MCLR NC OE OSC1 OSC2 I/O Descriptions (Continued) Pin Type I I I O I I/P -- O I O Buffer Type ST ST ST -- Analog ST -- -- ST/CMOS -- Description External Interrupt0 External Interrupt1 External Interrupt2 System bus low byte strobe Low voltage detect input Master clear (reset) input or programming voltage input. This pin is an active low reset to the device. These pins should be left unconnected. System bus output enable strobe Oscillator crystal input or external clock source input. ST buffer when configured in RC mode. CMOS otherwise. Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT, which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. Parallel Slave Port for interfacing to a microprocessor port. These pins have TTL input buffers when PSP module is enabled.
PSP0 PSP1 PSP2 PSP3 PSP4 PSP5 PSP6 PSP7 RA0 RA1 RA2 RA3 RA4 RA5 RA6
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL ST TTL TTL
PORTA is a bi-directional I/O port.
RA4 is an open drain when configured as output.
4
PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
Architecture
Interrupt on change pin. Interrupt on change pin. Interrupt on change pin. Serial programming clock. TTL input buffer as general purpose I/O, Schmitt Trigger input buffer when used as the serial programming clock. RB7 I/O TTL/ST Interrupt on change pin. Serial programming data. TTL input buffer as general purpose I/O, Schmitt Trigger input buffer when used as the serial programming data. Legend: TTL = TTL-compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels O = output PU = Weak internal pull-up I = input Analog = Analog input or output P = Power
RB0 RB1 RB2 RB3 RB4 RB5 RB6
I/O I/O I/O I/O I/O I/O I/O
TTL TTL TTL TTL TTL TTL TTL/ST
2000 Microchip Technology Inc.
DS39504A-page 4-9
PIC18C Reference Manual
Table 4-1: Pin Name I/O Descriptions (Continued) Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Buffer Type ST ST ST ST ST ST ST ST TTL ST ST ST ST ST ST ST ST PORTE is a bi-directional I/O port. RE0 RE1 RE2 RE3 RE4 RE5 RE6 RE7 ST ST ST ST ST ST ST ST PORTF is a digital input RF0 I/O ST RF1 I/O ST RF2 I/O ST RF3 I/O ST RF4 I/O ST RF5 I/O ST RF6 I/O ST RF7 I/O ST Legend: TTL = TTL-compatible input ST = Schmitt Trigger input with CMOS levels PU = Weak internal pull-up Analog = Analog input or output Description PORTC is a bi-directional I/O port. RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 RD RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7
Read control for parallel slave port. (See also WR and CS pins.) PORTD is a bi-directional I/O port.
CMOS = CMOS compatible input or output O = output I = input P = Power
DS39504A-page 4-10
2000 Microchip Technology Inc.
Section 4 Architecture
Table 4-1: Pin Name I/O Descriptions (Continued) Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Buffer Type ST ST ST ST ST ST ST ST PORTH is a digital input RH0 RH1 RH2 RH3 RH4 RH5 RH6 RH7 RJ0 RJ1 RJ2 RJ3 RJ4 RJ5 RJ6 RJ7 ST ST ST ST ST ST ST ST PORTJ is a digital input ST ST ST ST ST ST ST ST digital input Description PORTG is a digital input RG0 RG1 RG2 RG3 RG4 RG5 RG6 RG7
PORTK is a RK0 I/O ST RK1 I/O ST RK2 I/O ST RK3 I/O ST RK4 I/O ST RK5 I/O ST RK6 I/O ST RK7 I/O ST Legend: TTL = TTL-compatible input ST = Schmitt Trigger input with CMOS levels PU = Weak internal pull-up Analog = Analog input or output
4
Architecture
CMOS = CMOS compatible input or output O = output I = input P = Power
2000 Microchip Technology Inc.
DS39504A-page 4-11
PIC18C Reference Manual
Table 4-1: Pin Name I/O Descriptions (Continued) Pin Type Buffer Type Description
PORTL is a digital input RL0 I/O ST RL1 I/O ST RL2 I/O ST RL3 I/O ST RL4 I/O ST RL5 I/O ST RL6 I/O ST RL7 I/O ST RX I ST USART Asynchronous Receive SCL I/O ST Synchronous serial clock input/output for I2C mode. SCLA I/O ST Synchronous serial clock for I2C interface. SCLB I/O ST Synchronous serial clock for I2C interface. SDA I/O ST I2CTM Data I/O SDAA I/O ST Synchronous serial data I/O for I2C interface SDAB I/O ST Synchronous serial data I/O for I2C interface SCK I/O ST Synchronous serial clock input/output for SPI mode. SDI I ST SPI Data In SDO O -- SPI Data Out (SPI mode) I ST SPI Slave Select input SS T0CKI I ST Timer0 external clock input T1CKI I ST Timer1 external clock input T1OSO O CMOS Timer1 oscillator output T1OSI I CMOS Timer1 oscillator input TX O -- USART Asynchronous Transmit (See related RX) O -- System bus upper byte strobe UB Legend: TTL = TTL-compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels O = output PU = Weak internal pull-up I = input Analog = Analog input or output P = Power
DS39504A-page 4-12
2000 Microchip Technology Inc.
Section 4 Architecture
Table 4-1: Pin Name VREF I/O Descriptions (Continued) Pin Type I Buffer Type Analog Description
Analog High Voltage Reference input. DR reference voltage output on devices with comparators. VREF+ I Analog Analog High Voltage Reference input. Usually multiplexed onto an analog pin. VREFI Analog Analog Low Voltage Reference input. Usually multiplexed onto an analog pin. VSS P -- Ground reference for logic and I/O pins. VDD P -- Positive supply for logic and I/O pins. P -- Programming voltage input VPP I TTL Write control for parallel slave port (See CS and RD pins also). WR O -- System bus write low byte strobe WRL O -- System bus write high byte strobe WRH Legend: TTL = TTL-compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels O = output PU = Weak internal pull-up I = input Analog = Analog input or output P = Power
4
Architecture
2000 Microchip Technology Inc.
DS39504A-page 4-13
PIC18C Reference Manual
4.5 Design Tips
No related design tips at this time.
DS39504A-page 4-14
2000 Microchip Technology Inc.
Section 4 Architecture
4.6 Related Application Notes
This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the Enhanced family (that is, they may be written for the Base-Line, the Mid-Range, or High-End families), but the concepts are pertinent and could be used (with modification and possible limitations). The current application notes related to Architecture are: Title No related application notes at this time. Application Note #
Note:
Please visit the Microchip Web site for additional software code examples. These code examples are stand alone examples to assist in the understanding of the PIC18CXXX. The web address for these examples is: http://www.microchip.com/10/faqs/codeex/
4
Architecture
2000 Microchip Technology Inc.
DS39504A-page 4-15
PIC18C Reference Manual
4.7 Revision History Revision A
This is the initial released revision of the Enhanced MCU Architecture description.
DS39504A-page 4-16
2000 Microchip Technology Inc.

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